Power consumption optimization and delay based on ant colony algorithm in network-on-chip
Keywords:
network-on-chip, optimization, power consumption, delay on chipAbstract
With a further increase of the number of on-chip devices, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new NoC structure to
solve the interconnection of an on-chip device. For the purpose of improving the performance of a network-on-chip without a significant increase in
power consumption, the paper proposes a networkon-chip that selects NoC (Network-On-Chip) platform with 2-dimension mesh as the carrier and incorporates communication power consumption and delay into a unified cost function. The paper uses ant colony optimization for the realization of NoC map facing power consumption and delay potential. The experiment indicates that in
comparison with a random map, single objective optimization can separately account for (30%~47%) and (20%~39%) of communication power consumption and execution time, and joint objective optimization can further excavate the
potential of time dimension in a mapping scheme dominated by the power.
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